1. Field of the Invention
The present invention relates to a semiconductor memory device that simultaneously accesses multiple bits of data and a memory access method for the semiconductor memory device.
Priority is claimed on Japanese Patent Application No. 2008-184974, filed Jul. 16, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Generally, a semiconductor memory device includes: memory cells arranged in a matrix; multiple Mats (memory cell mats) arranged in a matrix, each of which includes multiple memory cells; multiple SAs (first amplifier circuits) connected to the memory cells through bit lines; and multiple DA/WAs (second amplifier circuits) connected to the SAs through LIOs (local input/output lines).
Each DA/WA is connected to an external terminal through an MIO (main input/output line), and includes: a DA (reading circuit) that reads out data from a memory cell, amplifies the read data, and outputs the amplified data; and a WA (writing circuit) that amplifies input data and writes the amplified data to a memory cell.
To reduce the area of a semiconductor chip, some semiconductor memory devices are configured to include DA/WA at a region where an SWD (subword driver) row including SWDs that drive subword lines connected to memory cells included in each Mat crosses an ST (first amplifier circuit column) including multiple SAs, as shown in FIG. 5.
An ST includes SAs, DA/WAs, and SWC2s (power supply circuit) arranged in series in the vertical direction. The SWD row extends in a direction parallel to bit lines (horizontal direction). An ST extends in a direction parallel to LIOs (vertical direction).
Hereinafter, the case where the semiconductor memory device reads out data from a memory cell by one operation of data inputting/outputting (memory access) is explained with reference to FIG. 6.
Based on a row address of an input address, one of MTs (memory cell mat columns) extending in a direction parallel to LIOs (vertical direction) is activated by an XDEC (X decoder) (not shown), and the remaining MTs are inactivated.
Assuming that MT1 shown in FIG. 6 is selected, data stored in memory cells included in the activated MT1 are output to the corresponding SAs through bit lines connecting the memory cells and the corresponding SAs, and thereby STs are activated. In this case, data are output from MT1 to both ST1 (provided on the left side of MT1) and ST2 (provided on the right side of MT1), and thereby ST1 and ST2 are activated.
Then, a YDEC (Y decoder) turns on a Y switch (not shown) based on a column address of the input address, and thereby data are output from an SA connected to one side of the Y switch to an LIO connected to the other side of the Y switch.
In this case, it is assumed that 4 bits of data are output from respective four cells included in MT1. Specifically, two bits of data are output toward the right side and the remaining 2 bits of data are output toward the left side.
Then, each DA/WA amplifies the data read out to the connected LIO and outputs the amplified data to a corresponding MIO. In this case, each of DA/WA1 to DA/WA4 outputs 1 bit of data, i.e., total 4 bits of data are output from DA/WA1 to DA/WA4 through MIO1 to MIO4.
As explained above, the amount of data to be input/output by one operation of inputting/outputting, i.e., one memory access is limited in the semiconductor memory device shown in FIG. 6. In other words, the number of MIOs is limited according to the number of DA/WAs included in each ST. Specifically, the number of MIOs is twice that of DA/WAs included in each ST.
This is because STn and ST(n+1) which are on both sides of MTn are activated by one operation of data inputting/outputting, and then data are output from MTn to DA/WAn and DA/WA(n+2) included in STn, and DA/WA(n+1) and DA/WA(n+3) included in ST(n+1).
Therefore, faster writing/reading of data to/from the semiconductor memory device can be implemented by increasing the number of DA/WAs included in one ST so that the number of MIOs and the number of bits to be simultaneously read out increase.
However, the area of a region where an ST crosses an SWD row, i.e., the region where a DA/WA is provided, is limited. In other words, the number of DA/WAs that can be provided in the region is limited depending on the area of the region.
For this reason, when the number of MIOs is increased in the semiconductor device shown in FIG. 6, it is necessary to increase the division number of memory cell mats, i.e., the number of regions where STs cross SWD rows, i.e., regions where DA/WAs are provided.
As a method of increasing the number of MIOs included in a semiconductor memory device, Japanese Unexamined Patent, First Publication No. 2000-49305 discloses a configuration in which DA/WAs are provided outside of a memory cell matrix.
However, the increase in the number of regions where DA/WAs are provided causes an increase in the area of a semiconductor chip.
Additionally, in the configuration disclosed in Japanese Unexamined Patent, First Publication No. 2000-49305, a DA/WA is provided outside of the memory cell matrix, not in a region where an ST crosses an SWD row, thereby making a semiconductor chip larger than in the configuration in which a DA/WA is provided in a region where an ST crosses an SWD row. Further, the number of DA/WAs to be provided outside of the memory cell matrix increases as the number of MIOs increases, thereby increasing the area of the semiconductor chip.